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coolset?-f3 ice3b0365l ICE3A1065L ice3a1565l off-line smps current mode controller with integrated 650v startup cell/depletion coolmos? and latched off mode never stop thinking. power management & supply version 2.0, 8 may 2006
edition 2006-05-08 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 1999. all rights reserved. attention please! the information herein is given to describe certain com ponents and shall not be considered as warranted charac- teristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warrant ies, including but not limited to warran ties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and co nditions and prices please contact your nearest infi- neon technologies office in germany or our infineon tec hnologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or system s with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representat ives worldwide: see our webpage at http:// www.infineon.com coolmos?, coolset? are trademarks of infineon technologies ag. coolset? -f3 ice3xxx65l revision history: 2006-05-08 datasheet previous version: 1.0 ( ice3a106 5l/ice3a1565l ), 1.2 ( ice3b0365l ) page subjects (major changes since last revision) group ice3b0365l, ICE3A1065L and ice3a1565l together 11, 12, 13 revise typo to trigger level at fb ( c5 ) 15 revise pulse drain current 20 add temperature derating curve 3, 23 add marking 25 add pcb layout recommendation
type package marking v ds f osc r dson 1) 1) typ @ t=25c 230vac 15% 2) 2) calculated maximum input power rating at t a =75c, t j =125c and without copper area as heat sink. 85-265 vac 2) ice3b0365l ICE3A1065L ice3a1565l pg-dip-8-6 pg-dip-8-6 pg-dip-8-6 ice3b0365l ICE3A1065L ice3a1565l 650v 650v 650v 67khz 100khz 100khz 6.45 2.95 1.70 22w 32w 42w 10w 16w 20w version 2.0 3 8 may 2006 coolset? -f3 ice3xxx65l off-line smps current mode controller with integrated 650v startup cell/depletion coolmos? and latched off mode test pg-dip-8-6 description the new generation coolset?-f3 controller provides active burst mode to reach the lowest standby power requirements <100mw at no load. as the controller is always active during active burst mode, there is an immediate response on load jumps without any black out in the smps. in active burst mode the ripple of the output voltage can be reduced <1%. furthermore, to increase the robustness and safety of the system, the device enters into latched off mode in t he cases of overtemperature, overvoltage or short winding. the latched off mode can only be reset by disconnecting the main line. auto restart mode is entered for cases like open loop or overload. by means of an internal precise peak current limitation, the dimension of the transformer and the secondary diode can be lowered which leads to more cost efficiency. an adjustable blanking window prev ents the ic from entering auto restart mode or active burst mode unintentionally in case of high load jumps. product highlights ? active burst mode to reach the lowest standby power requirements < 100mw ? latched off mode and auto restart mode to increase robustness and safety of the system ? adjustable blanking window for high load jumps to increase system reliability ? pb-free lead plating dip package; rohs compilant features ? 650v avalanche rugged coolmos? with built in switchable startup cell ? active burst mode for lowest standby power @ light load controlled by feedback signal ? fast load jump response in active burst mode ? 67/100khz internally fixed switching frequency ? latched off mode for overtemperature detection ? latched off mode for overvoltage detection ? latched off mode for short winding detection ? auto restart mode for overload and open loop ? auto restart mode for vcc undervoltage ? blanking window for shor t duration high current ? user defined soft start ? minimum of external components required ? max duty cycle 72% ? overall tolerance of current limiting < 5% ? internal pwm leading edge blanking ? soft driving for low emi c softs c vcc c bulk converter dc output + snubber power management pwm controller current mode 85 ... 270 vac typical application r sense softs fb gnd active burst mode latched off mode auto restart mode control unit - cs vcc startup cell precise low tolerance peak current limitation drain coolset?-f3 with latch off mode coolmos?
coolset?-f3 ice3xxx65l table of contents page version 2.0 4 8 may 2006 1 pin configurati on and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin configuration with pg-dip-8 -6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 representative blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.2 pwm-latch ff1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5.1 leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5.2 propagation delay com pensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.6 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6.1 adjustable blanking window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6.2 active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.2.1 entering active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.2.2 working in active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.2.3 leaving active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6.3 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.3.1 latched off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.3.2 auto restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.1 absolute maximum rating s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.3.4 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3.5 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.3.6 coolmos? section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5 temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 7 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 8 schematic for recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . .25
version 2.0 5 8 may 2006 coolset?-f3 ice3xxx65l pin configurati on and functionality 1 pin configuration and functionality 1.1 pin configuration with pg-dip-8-6 figure 1 pin configuration pg-dip-8-6(top view) note: pin 4 and 5 are shorted within the dip 8 package. 1.2 pin functionality softs (soft start & au to restart control) the softs pin combines the functions of soft start during start up and error detection for auto restart mode. these functions are implemented and can be adjusted by means of an external capacitor at softs to ground. this capacitor also provides an adjustable blanking window for high load jumps, before the ic enters into auto restart mode. fb (feedback) the information about the re gulation is provided by the fb pin to the internal protec tion unit and to the internal pwm-comparator to control the duty cycle. the fb- signal controls in case of light load the active burst mode of the controller. cs (current sense) the current sense pin senses the voltage developed on the series resistor inserted in the source of the integrated depl. coolmos?. if cs reaches the internal threshold of the current limit comparator, the driver output is immediately switched off. furthermore the current information is provided for the pwm- comparator to realize the current mode. drain (drain of integr ated depl. coolmos?) pin drain is the connection to the drain of the internal depl. coolmos tm . vcc (power supply) the vcc pin is the positive supply of the ic. the operating range is between 8.5v and 21v. gnd (ground) the gnd pin is the ground of the controller. pin symbol function 1 softs soft-start 2 fb feedback 3 cs current sense/ 650v 1) depl. coolmos? source 1) at t j = 110c 4drain 650v 1) depl. coolmos? drain 5drain 650v 1) depl. coolmos? drain 6 n.c. not connected 7 vcc controller supply voltage 8 gnd controller ground package pg-dip-8-6 1 6 7 8 4 3 2 5 gnd softs fb cs vcc n.c. drain drain
version 2.0 6 8 may 2006 coolset?-f3 ice3xxx65l representative blockdiagram internal bias voltage reference oscillator duty cycle max c11 x3.7 soft-start comparator current limiting pwm op current mode soft start c2 c1 21v 4.0v r fb power management c softs c vcc 85 ... 270 vac c bulk + converte r dc outp u v out spike blanking 8.0us pwm comparator c3 5.4v c4 4.8v r softs gate driver 0.72 clock r sense 0.85v 10k ? d1 t2 c6a 3.4v c5 1.30v c10 1.66v r s q auto restart mode & g7 & g5 & g9 1 g8 & g1 1 g3 thermal shutdown t j >140c 3.25k ? 4.4v s1 6.5v 1 t1 power-down reset latched off mode reset v vcc < 6v latched off mode cs softs gnd vcc c7 c8 fb pwm section control unit ff1 t3 c12 & 0.257v leading edge blanking 220ns 5k ? 10pf 6.5v g10 spike blanking 190 ns 1v 5k ? 1pf propagation-delay compensation 6.5v undervoltage lockout 15v 8.5v v csth g2 - ice3xxxxxl / coolset?-f3 with latched off mode snubber vcc drain coolmos? startup cell c6b & g6 4.0v & g11 active burst mode 2 representative blockdiagram figure 2 representative blockdiagram
version 2.0 7 8 may 2006 coolset?-f3 ice3xxx65l functional description 3 functional description all values which are used in the functional description are typical values. for calculating the worst cases the min/max values which can be found in section 4 electrical characteristics have to be considered. 3.1 introduction coolset?-f3 is the further development of the coolset?-f2 to meet the requirements for the lowest standby power at minimum load and no load conditions. a new fully in tegrated standby power concept is implemented into the ic in order to keep the application design easy. compared to coolset?-f2 no further external parts are needed to achieve the lowest standby power. an intelligent active burst mode is used for this standby mode. after entering this mode there is still a full control of the power conversion by the secondary side via t he same optocoupler that is used for the normal pwm control. the response on load jumps is optimized. the voltage ripple on v out is minimized. v out is further on well controlled in this mode. the usually external connected rc-filter in the feedback line after the optocoupler is integrated in the ic to reduce the external part count. furthermore a high voltage st artup cell is integrated into the ic which is switched off once the undervoltage lockout on-threshold of 15v is exceeded. this startup cell is part of the integrated depl. coolmos?. the external startup resistor is no longer necessary as this startup cell is connected to the drain. power losses are therefore reduced. this increases the efficiency under light load conditions drastically. the soft-start capacitor is also used for providing an adjustable blanking window for high load jumps. during this time window the overload detection is disabled. with this concept no further external components are necessary to adjust the blanking window. in order to increase the robustness and safety of the system, the ic provides 2 levels of protection modes: latched off mode and auto restart mode. the latched off mode is only entered under dangerous conditions which can damage the smps if not switched off immediately. a restart of the system can only be done by disconnecting the ac line. the auto restart mode reduces the average power conversion to a minimum under unsafe operating conditions. this is necessary for a prolonged fault condition which could otherw ise lead to a destruction of the smps over time. once the malfunction is removed, normal operation is automatically initiated after the next start up phase. the internal precise peak current limitation reduces the costs for the transformer an d the secondary diode. the influence of the change in the input voltage on the power limitation can be avoided together with the integrated propagation delay compensation. therefore the maximum power is nearly independent on the input voltage which is required for wide range smps. there is no need for an extra over-sizing of the smps, e.g. the transforme r or the secondary diode. 3.2 power management figure 3 power management the undervoltage lockout monitors the external supply voltage v vcc . when the smps is plugged to the main line the internal startup cell is biased and starts to charge the external capacitor c vcc which is connected to the vcc pin. this vcc charge current which is provided by the startup cell from the drain pin is 1.05ma. when v vcc exceeds the on-threshold v ccon =15v the internal voltage reference and bias circuit are switched on. then the startup cell is switched off by the undervoltage lockout and therefore no power losses present due to the connection of the startup ce ll to the drain voltage. to avoid uncontrolled ringing at switch-on a hysteresis is implemented. the switch-off of the controller can only take place after active mode was entered and v vcc falls below 8.5v. internal bias voltage reference power management latched off mode reset v vcc < 6v 6.5v latched off mode undervoltage lockout 15v 8.5v t1 power-down reset softs active burst mode auto restart mode startup cell vcc drain depl. coolmos?
coolset?-f3 ice3xxx65l functional description version 2.0 8 8 may 2006 the maximum current consumption before the controller is activated is about 160 a. when v vcc falls below the off-threshold v ccoff =8.5v the internal reference is switched off and the power down reset let t1 discharging the soft-start capacitor c softs at pin softs. thus it is ensured that at every startup cycle the voltage ramp at pin softs starts at zero. the internal voltage reference is switched off if latched off mode or auto restart mode is entered. the current consumption is then reduced to 300 a. once the malfunction condition is removed, this block will then turn back on. the recovery from auto restart mode does not require disconnecting the smps from the ac line. in case latched off mode is entered, vcc needs to be lowered below 6v to reset the latched off mode. this is done usually by disconnecting the smps from the ac line. when active burst mode is entered the internal bias is switched off in order to reduce the current consumption below 1.05ma while keeping the voltage reference still active as this is necessary in this mode. 3.3 startup phase figure 4 soft start at the beginning of the star tup phase, the ic provides a soft start duration whereby it controls the maximum primary current by means of a duty cycle limitation. a signal v softs which is generated by the external capacitor c softs in combination with the internal pull up resistor r softs , determines the duty cycle until v softs exceeds 4v. when the soft start begins, c softs is immediately charged up to approx. 1v by t2. therefore the soft start phase takes place between 1v and 4v. above v softss = 4v there is no longer duty cycle limitation dc max which is controlled by comparator c7 since comparator c2 blocks the gat e g7 (see figure 4). this maximum charge current in the very first stage when v softs is below 1v, is limited to 1.30ma. figure 5 startup phase by means of this extra charge stage, there is no delay in the beginning of the startup phase when there is still no switching. furthermore soft start is finished at 4v to have faster the maximum po wer capability. the duty cycles dc 1 and dc 2 are depending on the mains and the primary inductance of the transformer. the limitation of the primary current by dc 2 is related to v softs = 4v. but dc 1 is related to a maximum primary current which is limited by the internal current limiting with cs = 1v. therefore the maximum startup phase is divided into a soft start phase until t1 and a phase from t1 until t2 where ma ximum power is provided if demanded by the fb signal. soft-start comparator soft start & g7 c7 c softs r softs t2 3.25k 6.5v t3 1v softs gate driver 0.85v x3.7 pwm op cs 4v c2 dc max dc 1 dc 2 t t v softs max. soft start phase 1v 4v 5.4v max. startup phase t1 t2
coolset?-f3 ice3xxx65l functional description version 2.0 9 8 may 2006 3.4 pwm section figure 6 pwm section block 3.4.1 oscillator the oscillator generates a fixed frequency. the switching frequency for ice3axx65l is f osc = 100khz and ice3bxx65l is f osc = 67khz. a resistor, a capacitor and a current source and current sink which determine the frequency are integrated. the charging and discharging current of the implemented oscillator capacitor are internally tri mmed, in order to achieve a very accurate switching frequency. the ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of d max =0.72. 3.4.2 pwm-latch ff1 the oscillator clock output provides a set pulse to the pwm-latch when initiating the internal coolmos? conduction. after setting the pwm-latch can be reset by the pwm comparator, the soft start comparator or the current-limit co mparator. in case of resetting, the driver is shut down immediately. 3.4.3 gate driver figure 7 gate driver the driver-stage is optimized to minimize emi and to provide high circuit efficiency. this is done by reducing the switch on slope when exceeding the internal coolmos? threshold. this is achieved by a slope control of the rising edge at the driver?s output (see figure 8). figure 8 gate rising slope thus the leading switch on spike is minimized. when the integrated coolmos? is switched off, the falling shape of the driver is slowed down when reaching 2v to prevent an overshoot below ground. furthermore the driver circuit is designed to eliminate cross conduction of the output stage. during powerup when vcc is below the undervoltage lockout threshold v vccoff , the output of the gate driver is low to disable power transfer to the secondary side. oscillator duty cycle max gate driver 0.72 clock & g9 1 g8 pwm section ff1 r s q soft start comparator pwm comparator current limiting internal coolmos? gate vcc 1 pwm-latch coolmos? gate driver gate t (internal) v gate 5v ca. t = 130ns
coolset?-f3 ice3xxx65l functional description version 2.0 10 8 may 2006 3.5 current limiting figure 9 current limiting block there is a cycle by cycle current limiting realized by the current-limit comparator c10 to provide an overcurrent detection. t he source current of the internal coolmos? is sensed via an external sense resistor r sense . by means of r sense the source current is transformed to a sense voltage v sense which is fed into the pin cs. if the voltage v sense exceeds the internal threshold voltage v csth the comparator c10 immediately turns off the gate drive by resetting the pwm latch ff1. a propagation delay compensation is added to support the immediate shut down without delay of the internal coolmos? in case of current limiting. the influence of the ac input voltage on the maximum output power can thereby be avoided. to prevent the current limi ting from distortions caused by leading edge spikes a leading edge blanking is integrated in the current sense path for the comparators c10, c12 and the pwm-op. the output of comparator c12 is activated by the gate g10 if active burst mode is entered. once activated the current limiting is thereby reduced to 0.257v. this voltage level determines the power level when the active burst mode is left if there is a higher power demand. a further comparator c11 is implemented to detect dangerous current levels which could occur if there is a short winding in the transf ormer or the secondary diode is shorten. to ensure that there is no accidentally entering of the latched mode by the comparator c11 a spike blanking with 190ns is integrated in the output path of comparator c11. 3.5.1 leading edge blanking figure 10 leading edge blanking each time when the inte rnal coolmos? is switched on, a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. this spike can cause the gate drive to switch off unintentionally. to avoid a premature termination of the switching pu lse, this spike is blanked out with a time constant of t leb = 220ns. during this time, the gate drive will not be switched off. 3.5.2 propagation delay compensation in case of overcurrent detect ion, the switch-off of the internal coolmos? is delayed due to the propagation delay of the circuit. this delay causes an overshoot of the peak current i peak which depends on the ratio of di/ dt of the peak current (see figure 11). figure 11 current limiting the overshoot of signal2 is bigger than of signal1 due to the steeper rising waveform. this change in the slope is depending on the ac input voltage. propagation delay compensation is integrated to limit the overshoot dependency on di/dt of the rising primary c11 current limiting c10 1.66v c12 & 0.257v leading edge blanking 220ns g10 spike blanking 190 ns propagation-delay compensation v csth active burst mode pwm latch ff1 10k d1 1pf pwm-op cs latched off mode t v sense v csth t leb = 220ns t i sense i limit t propagation delay i overshoot1 i peak1 signal1 signal2 i overshoot2 i peak2
coolset?-f3 ice3xxx65l functional description version 2.0 11 8 may 2006 current. that means the propagation delay time between exceeding the current sense threshold v csth and the switch off of the internal coolmos? is compensated over temperat ure within a wide range. current limiting is now possible in a very accurate way. e.g. i peak = 0.5a with r sense = 2. without propagation delay compensation the current sense threshold is set to a static voltage level v csth =1v. a current ramp of di/dt = 0.4a/s, that means dv sense /dt = 0.8v/s, and a propagation delay time of i.e. t propagation delay =180ns leads then to an i peak overshoot of 14.4%. by means of propagation delay compensation the overshoot is only about 2% (see figure 12). figure 12 overcurrent shutdown the propagation delay compensation is realized by means of a dynamic threshold voltage v csth (see figure 13). in case of a steeper slope the switch off of the driver is earlier to compensate the delay. figure 13 dynamic voltage threshold v csth 3.6 control unit the control unit contains the functions for active burst mode, auto restart mode and latched off mode. the active burst mode and the auto restart mode are combined with an adjustable blanking window which is depending on the external soft start capacitor. by means of this adjustable blanking window, the ic avoids entering into these two modes accidentally. furthermore it also provides a certain time whereby the overload detection is delayed. this delay is useful for applications which normally works with a low current and occasionally require a short duration of high current. 3.6.1 adjustable blanking window figure 14 adjustable blanking window v softs is clamped at 4.4v by the closed switch s1 after the smps is settled. if overload occurs v fb is exceeding 4.8v. auto restart mode can?t be entered as the gate g5 is still blocked by the comparator c3. but after v fb has exceeded 4.8v the switch s1 is opened via the gate g2. the external soft start capacitor can now be charged further by the integrated pull up resistor r softs . the comparator c3 releases the gates g5 and g6 once v softs has exceeded 5.4v. therefore there is no entering of auto restart mode possible during this charging time of the external capacitor 0,9 0,95 1 1,05 1,1 1,15 1,2 1,25 1,3 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 with compensation without compensation d t dv sense s v sense v v t v csth v osc signal1 signal2 v sense propagation delay max. duty cycle off time t c3 5.4v c4 4.8v c6 1.30v & g5 & g6 4.4v s1 & g4 1 g2 control unit 5k ? active burst mode auto restart mode r softs 6.5v softs fb
coolset?-f3 ice3xxx65l functional description version 2.0 12 8 may 2006 c softs . the same procedure happens to the external soft start capacitor if a lo w load condition is detected by comparator c5 when v fb is falling below 1.30v. only after v softs has exceeded 5.4v and v fb is still below 1.30v active burs t mode is entered. 3.6.2 active burst mode the controller provides active burst mode for low load conditions at v out . active burst mode increases significantly the efficiency at light load conditions while supporting a low ripple on v out and fast response on load jumps. during active burst mode which is controlled only by the fb signal the ic is always active and can therefore immediately response on fast changes at the fb signal. the startup cell is kept switched off to avoid increased power losses for the self supply. figure 15 active burst mode the active burst mode is located in the control unit. figure 15 shows the related components. 3.6.2.1 entering active burst mode the fb signal is always observed by the comparator c5 if the voltage level falls below 1.30v. in that case the switch s1 is released which allows the capacitor c softs to be charged starting from the clamped voltage level at 4.4v in normal operating mode. if v softs exceeds 5.4v the comparator c3 releases the gate g6 to enter the active burst mode. the time window that is generated by combining the fb and softs signals with gate g6 avoids a sudden entering of the active burst mode due to large load jumps. this time window can be adjusted by the external capacitor c softs . after entering active burst mode a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the ic down to approx. 1.05ma. in this off state phase the ic is no longer self supplied so that therefore c vcc has to provide the vcc current (see figure 16). furthermore gate g11 is then released to start the next burst cycle once v fb has 3.4v exceeded. it has to be ensured by the application that the vcc remains above the undervoltage lockout level of 8.5v to avoid that the startup ce ll is accidentally switched on. otherwise power losses are significantly increased. the minimum vcc level during active burst mode is depending on the load conditions and the application. the lowest vcc level is reac hed at no load conditions at v out . 3.6.2.2 working in active burst mode after entering the active burst mode the fb voltage rises as v out starts to decrease due to the inactive pwm section. comparator c6a observes the fb signal if the voltage level 4v is exceeded. in that case the internal circuit is again acti vated by the internal bias to start with switching. as now in active burst mode the gate g10 is released the current limit is only 0.257v to reduce the conduction losses and to avoid audible noise. if the load at v out is still below the starting level for the active burst mode the fb signal decreases down to 3.4v. at this level c6b deactivates again the internal circuit by switching off the internal bias. the gate g11 is released as af ter entering active burst mode the burst flag is set. if working in active burst mode the fb voltage is changing like a saw tooth between 3.4v and 4v (see figure 16). 3.6.2.3 leaving active burst mode the fb voltage immediately in creases if there is a high load jump. this is observed by comparator c4. as the current limit is ca. 26% during active burst mode a certain load jump is needed that fb can exceed 4.8v. at this time c4 resets the active burst mode which also c3 5.4v c4 4.8v c6a 4.0v 1.30v fb control unit active burst mode 4.4v s1 5k ? internal bias r softs 6.5v softs & g10 current limiting & g6 c6b 3.4v & g11 c5
coolset?-f3 ice3xxx65l functional description version 2.0 13 8 may 2006 blocks c12 by the gate g10. maximum current can now be provided to stabilize v out . figure 16 signals in active burst mode 3.6.3 protection modes the ic provides several protection features which are separated into two categories. some enter latched off mode, the others enter auto restart mode. the latched off mode can only be reset if vcc is falling below 6v. both modes prevent the smps from destructive states. the following table shows the relationship between possible system failures and the chosen protection modes. 3.6.3.1 latched off mode figure 17 latched off mode the vcc voltage is observed by comparator c1 if 21v is exceeded. the output of c1 is combined with the output of c4 which observes fb signal if 4.8v is 1.30v 4.00v 4.80v v fb 4.40v 5.40v v softs t t 0.257v 1.00v v cs 8.5v v vcc t t 1.05ma i vcc t 7.2ma v out t max. ripple < 1% blanking window current limit level during active burst mode 3.40v entering active burst mode leaving active burst mode vcc overvoltage latched off mode overtemperature latched off mode short winding/short diode latched off mode overload auto restart mode open loop auto restart mode vcc undervoltage auto restart mode short optocoupler auto restart mode c1 28v spike blanking 8.0us 1 g3 thermal shutdown t j >140c latched off mode vcc c11 1.70v spike blanking 190 ns cs voltage reference control unit latched off mode reset v vcc < 6v
coolset?-f3 ice3xxx65l functional description version 2.0 14 8 may 2006 exceeded. therefore the overvoltage detection is only activated if the fb signal is outside the operating range > 4.8v, e.g. when open loop happens. this means any small voltage overshoots of v vcc during normal operating can not start the latched off mode. the internal voltage reference is switched off once latched off mode is entered in order to reduce the current consumption of the ic as much as possible. latched off mode can only be reset by decreasing v vcc < 6v. in this stage, only the uvlo is working which controls the startup cell by switching on/off at v vccon /v vccoff . during this phase, the average current consumption is only 300 a. as there is no longer a self- supply by the auxiliary winding, vcc drops. the undervoltage lockout switches on the integrated startup cell when vcc falls below 8.5v. the startup cell is switched off again when vcc has exceeded 15v. once the latched off mode was entered, there is no start up phase after vcc has exceeded the switch- on level of the undervoltage lockout. therefore vcc changes between the switch-on and switch-off levels of the undervoltage lockout with a saw tooth shape (see figure 18). figure 18 signals in latched off mode the thermal shutdown block monitors the junction temperature of the ic. after detecting a junction temperature higher than 140c, latched off mode is entered. the signals coming from the temperature detection and vcc overvoltage detection are fed into a spike blanking with a time constant of 8.0 s to ensure system reliability. furthermore, a short winding or short diode on the secondary side can be detected by the comparator c11 which is in parallel to the propagation delay compensated current limit comparator c10. in normal operating mode comparator c10 keeps the maximum level of the cs signal at 1v. if there is a failure such as short winding or short diode, c10 is no longer able to limit the cs signal at 1v. c11 detects then the over current and enters immediately the latched off mode to keep the smps in a safe stage. 3.6.3.2 auto restart mode figure 19 auto restart mode in case of overload or open loop, fb exceeds 4.8v which will be observed by c4. at this time s1 is released that v softs can increase. if v softs exceeds 5.4v which is observed by c3, auto restart mode is entered as both inputs of the gate g5 are high. in combining the fb and softs signals, there is a blanking window generated which prevents the system to enter auto restart mode due to large load jumps. this time window is the same as for the active burst mode and can therefore be adjusted by the external c softs . in case of vcc undervoltage, the ic enters into the auto restart mode and starts a new startup cycle. short optocoupler also leads to vcc undervoltage as there is no self supply after activating the internal reference and bias. in contrast to the latched off mode, there is always a startup phase with switching cycles in auto restart mode. after this start up phase, the conditions are again checked whether the failure mode is still present. normal operation is resumed once the failure mode is removed that had caused the auto restart mode. 8.5v t i vccstart t 1.05ma v out v vcc t.b.d c3 5.4v c4 4.8v & g5 4.4v s1 1 g2 control unit 5k ? auto restart mode r softs 6.5v softs fb voltage reference
version 2.0 15 8 may 2006 coolset?-f3 ice3xxx65l electrical characteristics 4 electrical characteristics note: all voltages are measured with respect to ground (p in 8). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings , which when being exceeded may lead to destruction of the integrated circuit. for the same reason make su re, that any capacitor that will be connected to pin 7 ( v cc) is discharged before assembling the application circuit. parameter symbol limit values unit remarks min. max. drain source voltage v ds -650v t j =110c pulse drain current, t p limited by t jmax ice3b0365l i d_puls1 -1.6a ICE3A1065L i d_puls2 -3.4a ice3a1565l i d_puls3 -6.1a avalanche energy, repetitive t ar limited by max. t j =150c 1) 1) repetitive avalanche causes additional po wer losses that can be calculated as p av = e ar * f ice3b0365l e ar1 -0.005mj ICE3A1065L e ar2 -0.07mj ice3a1565l e ar3 -0.15mj avalanche current, repetitive t ar limited by max. t j =150c ice3b0365l i ar1 -0.3a ICE3A1065L i ar2 -1.0a ice3a1565l i ar3 -1.5a vcc supply voltage v vcc -0.3 22 v fb voltage v fb -0.3 6.5 v softs voltage v softs -0.3 6.5 v cs voltage v cs -0.3 6.5 v junction temperature t j -40 150 c storage temperature t s -55 150 c thermal resistance junction -ambient r thja - 90 k/w pg-dip-8-6 esd capability(incl. drain pin) v esd - 3 kv human body model 2) 2) according to eia/jesd22-a114-b (dischar ging a 100pf capacitor through a 1.5k ? series resistor)
version 2.0 16 8 may 2006 coolset?-f3 ice3xxx65l electrical characteristics 4.2 operating range note: within the operati ng range the ic operates as described in the functional description. 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range t j from ? 25 c to 130 c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc = 15 v is assumed. parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccoff 20 v junction temperature of controller t jcon -25 130 c max value limited due to thermal shut down of controller junction temperature of coolmos? t jcoolmos -25 150 c parameter symbol limit values unit test condition min. typ. max. start up current i vccstart - 160 220 a v vcc =14v vcc charge current i vcccharge1 0.55 1.05 1.60 ma v vcc = 0v i vcccharge2 -0.88-ma v vcc =14v leakage current of start up cell and coolmos? i startleak -0.250 a v vcc =16v, v drain = 450v at t j =100c supply current with inactive gate i vccsup_ng -5.57.0ma supply current with active gate ice3b0365l i vccsup_g1 -5.57.0ma v softs = 4.4v i fb = 0, ICE3A1065L i vccsup_g2 -5.97.5ma ice3a1565l i vccsup_g3 -6.38.0ma supply current in latched off mode i vcclatch -300- a i fb = 0 i softs = 0 supply current in auto restart mode with inactive gate i vccrestart -300- a i fb = 0 i softs = 0 supply current in active burst mode with inactive gate i vccburst1 - 1.051.25ma v vcc =15v v fb = 3.7v, v softs = 4.4v i vccburst2 - 0.951.15ma v vcc = 9.5v v fb = 3.7v, v softs = 4.4v vcc turn-on threshold vcc turn-off threshold vcc turn-on/off hysteresis v vccon v vccoff v vcchys 14.2 8.0 - 15.0 8.5 6.5 15.8 9.0 - v v v
version 2.0 17 8 may 2006 coolset?-f3 ice3xxx65l electrical characteristics 4.3.2 internal voltage reference 4.3.3 pwm section parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v ref 6.37 6.50 6.63 v measured at pin fb i fb = 0 parameter symbol limit values unit test condition min. typ. max. fixed oscillator frequency ice3axx65l f osc_a1 92 100 108 khz f osc_a2 94 100 106 khz t j = 25c fixed oscillator frequency ice3bxx65l f osc_b1 61 67 73 khz f osc_b2 63 67 71 khz t j = 25c max. duty cycle d max 0.67 0.72 0.77 min. duty cycle d min 0- - v fb < 0.3v pwm-op gain a v 3.5 3.7 3.9 voltage ramp max level v max-ramp -0.85-v v fb operating range min level v fbmin 0.3 0.7 - v v fb operating range max level v fbmax - - 4.75 v cs=1v, limited by comparator c4 1) 1) the parameter is not subjected to production test - verified by de sign/characterization fb pull-up resistor r fb 16 20 27 k ? softs pull-up resistor r softs 39 50 62 k ?
version 2.0 18 8 may 2006 coolset?-f3 ice3xxx65l electrical characteristics 4.3.4 control unit note: the trend of all the voltage levels in the cont rol unit is the same regarding the deviation except v vccovp and v vccpd parameter symbol limit values unit test condition min. typ. max. deactivation level for softs comparator c7 by c2 v softsc2 3.85 4.00 4.15 v v fb > 5v clamped v softs voltage during normal operating mode v softsclmp 4.23 4.40 4.57 v v fb = 4v activation limit of comparator c3 v softsc3 5.20 5.40 5.60 v v fb > 5v softs startup current i softsstart -1.3-ma v softs = 0v over load & open loop detection limit for comparator c4 v fbc4 4.62 4.80 4.98 v v softs > 5.6v active burst mode level for comparator c5 v fbc5 1.23 1.30 1.37 v v softs > 5.6v active burst mode level for comparator c6a v fbc6a 3.85 4.00 4.15 v after active burst mode is entered active burst mode level for comparator c6b v fbc6b 3.25 3.40 3.55 v after active burst mode is entered overvoltage detection limit v vccovp 20 21 22 v v fb > 5v latched thermal shutdown 1) 1) the parameter is not subjected to production test - verified by de sign/characterization t jsd 130 140 150 c spike blanking t spike -8.0- s power down reset for latched mode v vccpd 4.0 6.0 7.5 v after latched off mode is entered
version 2.0 19 8 may 2006 coolset?-f3 ice3xxx65l electrical characteristics 4.3.5 current limiting 4.3.6 coolmos? section parameter symbol limit values unit test condition min. typ. max. peak current limitation (incl. propagation delay) v csth 0.97 1.02 1.07 v d v sense / d t = 0.6v/ s (see figure 12) peak current limitation during active burst mode v cs2 0.232 0.257 0.282 v leading edge blanking t leb -220-ns v softs = 4.4v cs input bias current i csbias -1.0 -0.2 0 a v cs =0v over current detection for latched off mode v cs1 1.570 1.66 1.764 v cs spike blanking for comparator c11 t csspike -190-ns parameter symbol limit va lues unit test condition min. typ. max. drain source breakdown voltage v (br)dss 600 650 - - - - v v t j = 25c t j = 110c drain source on-resistance ice3b0365l r dson1 - - 6.45 13.7 7.50 17.0 ? ? t j = 25c t j =125c 1) at i d = 0.3a 1) the parameter is not subjected to production test - verified by design/characterization ICE3A1065L r dson2 - - 2.95 6.60 3.42 7.56 ? ? t j = 25c t j =125c 1) at i d = 1.0a ice3a1565l r dson3 - - 1.70 3.57 1.96 4.12 ? ? t j = 25c t j =125c 1) at i d = 1.5a effective output capacitance, energy related ice3b0365l c o(er)1 -3.65- pf v ds = 0v to 480v ICE3A1065L c o(er)2 -7.0- pf ice3a1565l c o(er)3 -11.63- pf rise time t rise -30 2) 2) measured in a typical flyback converter application -ns fall time t fall -30 2) -ns
version 2.0 20 8 may 2006 coolset?-f3 ice3xxx65l temperature derating curve 5 temperature derating curve figure 20 safe operating area ( soa ) curve for ice3b03065l figure 21 safe operating area ( soa ) curve for ICE3A1065L safe operating area for ice3a(b)0365( l ) i d = f ( v ds ) parameter : d = 0, t c = 25deg.c 0.001 0.01 0.1 1 10 1 10 100 1000 v ds [v] i d [a] dc tp = 10ms tp = 0.01ms tp = 0.1ms tp = 1ms tp = 100ms safe operating area for ice3a(b)1065 (l) i d = f ( v ds ) parameter : d = 0, t c = 25deg.c 0.001 0.01 0.1 1 10 1 10 100 1000 v ds [v] i d [a] dc tp = 100ms t p = 0.1ms tp = 1ms tp = 10ms tp = 1000ms
version 2.0 21 8 may 2006 coolset?-f3 ice3xxx65l temperature derating curve figure 22 safe operating area ( soa ) curve for ice3a1565l figure 23 soa temperature derating coefficient curve safe operating area for ice3a(b)1565( l ) i d = f ( v ds ) parameter : d = 0, t c = 25deg.c 0.001 0.01 0.1 1 10 1 10 100 1000 v ds [v] i d [a] dc tp = 100ms tp = 0.1ms tp = 1ms tp = 10ms tp = 1000ms soa temperature derating coefficient curve for f3 & f2 coolset 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 junction temperature tc [deg.c] soa temperature derating coefficient [%]
version 2.0 22 8 may 2006 coolset?-f3 ice3xxx65l outline dimension 6 outline dimension figure 24 pg-dip-8-6 ( pb-free lead pl ating platic dual-in-line outline ) dimensions in mm pg-dip-8-6 (plastic dual in-line outline)
version 2.0 23 8 may 2006 coolset?-f3 ice3xxx65l marking 7marking figure 25 marking for ice3b0365l figure 26 marking for ICE3A1065L marking marking
version 2.0 24 8 may 2006 coolset?-f3 ice3xxx65l marking figure 27 marking for ice3a1565l marking
version 2.0 25 8 may 2006 coolset?-f3 ice3xxx65l schematic for recommended pcb layout 8 schematic for recommended pcb layout figure 28 schematic for recommended pcb layout general guideline for pcb layout design using f3 coolset (refer to figure 28): 1. ?star ground ?at bulk capacitor ground, c11: ?star ground ?means all primary dc grounds should be connected to the ground of bulk capacitor c11 separately in one point. it can reduce the switching noi se going into the sensitive pins of the coolset device effectively. the primary dc gr ounds include the followings. a. dc ground of the primary auxiliary winding in power transformer, tr1, and ground of c16 and z11. b. dc ground of the curr ent sense resistor, r12 c. dc ground of the coolset device, gnd pin of ic11; t he signal grounds from c13, c14, c15 and collector of ic12 should be connected to the gnd pin of ic11 and then ?star ?connect to the bulk capacitor ground. d. dc ground from bridge rectifier, br1 e. dc ground from the br idging y-capacitor, c4 2. high voltage traces clearance: high voltage traces should keep enough spacing to the nearby traces. otherwise, arcing would incur. a. 400v traces (positive rail of bulk capacitor c11) to nearby trace: > 2.0mm b. 600v traces (drain voltage of co olset ic11) to nearby trace: > 2.5mm 3. filter capacitor close to the controller ground: filter capacitors, c13, c14 and c15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. guideline for pcb layout design when >3kv lightni ng surge test applied (refer to figure 28): 1. add spark gap spark gap is a pair of saw-tooth like copper plate fa cing each other which can discharge the accumulated charge during surge test through the sharp point of th e saw-tooth plate. a. spark gap 3 and spark gap 4, input common mode choke, l1: gap separation is around 1.5mm (no safety concern) c11 bulk cap r11 d11 c12 ic12 r12 c13 c16 c15 c14 d13 r14 r23 r22 ic21 c23 r24 c22 r21 r25 gnd vo d21 c21 f3 coolset schematic for recommended pcb layout r13 z11 tr1 n l br1 c2 y-cap c3 y-cap c1 x-cap l1 fuse1 c4 y-cap gnd spark gap 3 spark gap 4 d11 spark gap 1 spark gap 2 fb cs gnd nc softs/bl vcc f3 drain coolset ic11 *
version 2.0 26 8 may 2006 coolset?-f3 ice3xxx65l schematic for recommended pcb layout b. spark gap 1 and spark gap 2, live / neutral to ground: these 2 spark gaps can be used when the lightning surge requirement is >6kv. 230vac input voltage application, the gap separation is around 5.5mm 115vac input voltage application, the gap separation is around 3mm 2. add y-capacitor (c2 and c3) in the live and neutral to ground even though it is a 2-pin input 3. add negative pulse clamping diode, d11 to the current sense resistor, r12: the negative pulse clamping diode can reduce the negati ve pulse going into the cs pin of the coolset and reduce the abnormal behavior of the coolset. the di ode can be a fast speed diode such as in4148. the principle behind is to drain the high surge voltage from live/neut ral to ground without passing through the sensitive components such as the primary controller, ic11.
version 2.0 27 8 may 2006 coolset?-f3 ice3xxx65l schematic for recommended pcb layout
qualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im denken und handeln gegenber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie berzeugen. quality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total quality in thought and deed, towards co-workers, suppliers and you, our customer. our guideline is ?do everything with zero defects?, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ? you will be convinced. http://www.infineon.com total quality management published by infineo n technologies ag

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